This invention relates to a magnetic memory device implemented using a magneto-resistance effect element containing a ferromagnetic substance for controlling the magnetization direction of the ferromagnetic substance, thereby writing and storing information, and a write current drive circuit and a write current drive method applied to the magnetic memory device.
Hitherto, volatile memory such as DRAM or SRAM has been used as general-purpose memory used with an information processing apparatus such as a computer or a mobile communication apparatus. Unless a current is always supplied to the volatile memory, all information stored in the memory is lost. Thus, a nonvolatile memory needs to be separatelly provided for storing information, and flash EEPROM, a hard disk unit, or the like is used. As information processing is speeded up, it is an important problem to speed up the nonvolatile memory. From another aspect of information apparatus development intended for recent ubiquitous computing, there is a high demand for developing high-speed nonvolatile memory as a key device.
MRAM (Magnetic Random-Access Memory) is known as an effective art for speeding up nonvolatile memory. The MRAM has storage cells implemented as magnetic elements, arranged like a matrix. The current commercially practical MRAM uses GMR (Giant Magneto-Resistive). The GMR is a phenomenon in which in a layered product having two ferromagnetic layers disposed with mutual easy axes of magnetization made in the same direction, the layers deposited on each other, the resistance value of the layered product becomes the minimum if the magnetization directions of the ferromagnetic layers are parallel along the easy axis of magnetization; the maximum if antiparallel. Each storage cell stores information as binary information “0” or “1” corresponding to either of the two states and the resistance difference related to the information is detected as current or voltage change, whereby the information is read. In the actual GMR element, two ferromagnetic layers are deposited with a nonmagnetic layer therebetween, and include a fixed layer with the magnetization direction fixed and a free layer (magnetic sensitive layer) with the magnetization direction changeable according to an external magnetic field.
In a magnetic element using TMR (Tunneling Magneto-Resistive), the resistance change rate can be made exceptionally large as compared with the GMR element. The TMR is a phenomenon in which in two ferromagnetic layers (a fixed layer with the magnetization direction fixed and a magnetic sensitive layer with the magnetization direction changeable, namely, a free layer) deposited with an extremely thin insulating layer therebetween, the tunnel current value flowing through the insulating layer changes according to the relative angle between their magnetization directions. That is, if the magnetization directions are parallel, the tunnel current becomes the maximum (the resistance value of the element becomes the minimum); if the magnetization directions are antiparallel, the tunnel current becomes the minimum (the resistance value of the element becomes the maximum). As a specific example of the TMR element, a layered structure of CoFe/Aloxide/CoFe is known, and its resistance change rate reaches 40% or more. The TMR element has high resistance and is easily matched with a semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET). From such advantages, TMR-MRAM can be easily put-into high output as compared with GMR-MRAM and enhancement of the storage capacity and the access speed is expected.
In both GMR-MRAM and TMR-MRAM, information is written according to a similar technique. That is, a current is allowed to flow into a conductor wire for inducing a magnetic field, and the magnetization direction of the free layer is changed by the current magnetic field. Accordingly, the relative magnetization directions between the ferromagnetic layers become parallel or antiparallel and the corresponding binary information is stored.
For example, TMR-MRAM in a related art has the following configuration: As shown in FIG. 26, each write word line 202 (and each read word line 203) and each write/read bit line 201 are disposed so as to be orthogonal to each other. Here, the write wires are collectively called write lines. Although not shown, in each intersection area, a TMR element 207 is disposed so as to be sandwiched therebetween, forming a storage cell. FIG. 27 shows the general configuration of the TMR element. Thus, the TMR element 207 is implemented as a layered product made up of a first magnetic layer 204 of a fixed layer, a tunnel barrier layer 205, and a second magnetic layer 206 of a free layer. The layered product is provided on one side with the bit line 201 and on an opposite side with the read word line 203 and the write word line 202.
In the described MRAM, storing information in one storage cell is controlling the magnetization direction of the second magnetic layer 206 of the storage cell to the direction responsive to the information. This is performed by allowing a current to flow into the bit line 201 and the write word line 202 placed so as to sandwich the storage cell into which the information is to be written. A magnetic field is induced into each current flowing into the write line and the magnetization direction of the second magnetic layer 206 changes according to the resultant magnetic field.
At the time, a write current is supplied into the write line from a write current drive circuit (current drive). FIG. 28 shows a configuration example of the current drive applied to the MRAM in the related art (referring to non-patent document “ISSCC 2000 Digest paper TA7.2”). The circuit is made up of a part for generating a pulse whose shape is defined based on the necessary write current value and a part for selecting the write line to write and sending the generated pulse thereto. Here, a reference signal generation section 211, a positive amplifier 213A, a negative amplifier 213B, a current direction selection section 214, a timing block 216, and a pulse width control section 217 correspond to the former part. A write line selection section 219 corresponds to the latter. The timing block 216 performs timing control of the pulse width control section 217 of a time switch with a timing signal input to a write signal input line 215 as a trigger. The write line selection section 219 selects the write line to which a pulse is to be supplied in response to a decode signal input to an address decode line 218; generally it is made up of a large number of switching elements corresponding to the write lines. One end of each write line is connected to the write line selection section 219 and another end of the write line is grounded.
In the circuit, a data signal line 212 (Din) is divided into two branches and both positive and negative amplification signals are generated by the positive amplifier 213A and the negative amplifier 213B at the branches and either of the amplification signals is selected by the current direction selection section 214. A reference signal is input from the reference signal generation section 211 to th e positive amplifier 213A and the negative amplifier 213B for adjusting the magnitude of the input signal to the reference value. The data signal is a high or low digital signal representing write data. In the circuit portion, for example, a high signal is simply amplified by the positive amplifier 213A, but a low signal is inverse-amplified to a negative-potential pulse by the negative amplifier 213B (amplified signal is selected); consequently, either of the positive and negative pulses each having the reference value as the magnitude is generated in response to the data signal. This pulse is adjusted to a predetermined pulse width responsive to the necessary current amount in the pulse width control section 217 to produce a write pulse. The write pulse is supplied through the write line selection section 219 to the write line responsive to the decode signal. At this time, if a positive write pulse is applied to the write line, a current flows through the write line toward ground; if a negative write pulse is applied to the write line, a current flows from ground toward the pulse supply end side.
Thus, in the related art, first the pulse shape and sign are adjusted, whereby a write pulse to supply any desired current amount in a predetermined direction of the write line is generated and then is supplied to the write line. FIG. 29A shows functionally the current drive in the related art. A constant current control section 300 represents a circuit element having a function of controlling the write current amount to a constant value in the described current drive including the reference signal generation section 211 (usually, the reference signal generation section 211 is insufficient to control the pulse height with accuracy and thus a circuit for finely adjusting the pulse voltage value is added).
The conventional art as mentioned above is shown in the non-patent document “ISSCC 2000 Digest paper TA7.2”.
However, in the actual MRAM, the resistance value varies from one write line to another. The resistance variations occur if the wiring length or shape differs in response to the position of each write line or because of a manufacturing error, etc. In the current drive in the related art, the write current once supplied to the write line is not controlled and thus the actually flowing current amount varies from one write line to another in response to the resistance value; this is a problem. That is, no matter how the current drive in the related art can control the write pulse with high accuracy, it does not include a function of adjusting the supplied current amount in response to the resistance value for each write line and thus the effect of the resistance variations cannot be removed and it is difficult to stably supply a constant current to the write line.
In the MRAM, a magnetic field for write is a current magnetic field induced to a write current and therefore the write state in the element (magnetization state) is determined by the strength of the magnetic field, namely, the magnitude of the write current. Thus, if the write current value is not constant, information cannot be stored in a stable state or cannot be read stably; it is possible to hinder operation stability.
As a technique of controlling the supplied current amount in response to the resistance value of each write line, for example, it is possible to control the current value constant downstream of the write current for making constant the current amount flowing into the whole write line. This means that the constant current control section 300 is placed on the ground side of the write line, as shown in FIG. 29B. However, the normal constant current circuit is a circuit using band gap reference made up of a transistor, a diode, etc., in which case the current direction is limited to one direction and it becomes impossible to allow a current to flow into one write line in both directions. If an attempt is made to allow a current to flow into the write circuitry in both directions, two write lines must be bundled and circuitry must be placed symmetrically as shown in FIG. 29C; however, it is not realistic because both the circuit structure and control become complicated. It may be said that controlling the write current in both directions is an indispensable condition in the current drive of the MRAM, and controlling the write current to a constant value must be accomplished after the condition is satisfied. However, it is not easy to realize a circuit for coping with both, and an effective solution technique is not yet proposed.
The current drive in the related art usually is built with CMOS (Complementary MOS). The CMOS has a feature of digital switching operation; it is well fitted to a logic section such as the current direction selection section 214 and a switch such as the write line selection section 219, but the circuit portion corresponding to the constant current control section 300 is an analog circuit and therefore it is difficult to construct the current drive with CMOS. Essentially, the MOSFET is a voltage control element. Therefore, in the current drive in the related art of the CMOS circuit, the direct control target is voltage and the current value must be controlled indirectly as the voltage value and the width of an input pulse are controlled; current control in the essential sense has not been performed. It is known that MOS elements involve comparatively large characteristic variations caused by manufacturing variations of the film thickness of a gate oxide film, etc. Thus, it is feared that the pulse shape may vary from one write line to another because of the effect of the characteristic variations.
Further, there is a problem of enlarging the circuit scale of the current drive as heavy use of CMOS is made. In addition, a circuit using band gap reference, for example, a current mirror circuit, etc., is built in the portion corresponding to the constant current control section 300, and the area of the current drive in the related art on a memory chip is innegligibly large. Since the circuit configuration itself is also complicate, a simplifying technique is demanded.